The present invention relates to a test method of a communication apparatus, and especially to a pseudo noise generating circuit for conducting a test of an error correcting function in combination of soft decision and an error correcting function after rake combining under Rayleigh fading environment.
Conventionally, soft decision error correction is used in mobile communication apparatuses, and as represented by a soft decision Viterbi decoder, it becomes to be an essential function because of its high coding gain.
Also, in recent years, adoption of a turbo code and so forth, which has a higher coding gain and gradually gets near a Shannon limit is being studied, and its importance is increasing.
However, a properly prepared method was not suitable for the test method.
For example, since a method which has been conventionally conducted is conducted by inserting a Rayleigh fading simulator on a radio circuit, a test cannot be conducted before passing through an RF circuit. In addition, since a measuring apparatus such as a phasing simulator is necessary, a method capable of conducting the test by means of a simple arrangement has been desired.
Usually, an arrangement of a mobile communication terminal can be roughly divided into a radio section (abbreviated to an RF section) and a baseband section. The baseband section and the RF section are often tested, respectively, independent of each other, and a final test is conducted by finally comparing individually tested parts with each other. Accordingly, retrograde workload can be reduced by extracting problems in the individual tests as much as possible and restricting the extraction of the problems to a minimum in the comparison test, and good efficiency can be obtained as a whole.
Also, in case of testing the soft decision error correcting function, since measurement of subtle error rate characteristic always receives interference due to other apparatus in an experimental room, it subject to be incorrect one which is not reproduced. In addition, the test in a subtle region requires a long time and causes us much anxiety.
It is an objective of the present invention to provide technology capable of detecting a problem at an early stage as much as possible, which was found in a final process.
Another objective of the present invention is to provide a circuit for accurately testing subtle error rate characteristic of a soft decision error correcting circuit without receiving interference from other apparatuses in an experimental room and so forth.
A further objective of the present invention is to test error rate characteristic of a soft decision error correcting circuit by means of a simple arrangement without need of a measurement apparatus such as a Rayleigh fading simulator.
A further objective of the present invention is to provide an efficient test circuit for a mobile communication terminal, in which even though an RF circuit does not exist, a soft decision error correcting circuit can be tested with a single baseband, and retrograde workload is less.
A multi-dimensional pseudo noise generating circuit for soft-decision decoding of the present invention for accomplishing the above-described objective has PN generating means for generating a signal of binary length code, a memory for storing a threshold level based on accumulative probability distribution function obtained by integrating predetermined probability density function is stored, address generating means for generating an address of the above-described memory, and comparison means for comparing a data read from the above-described memory with the binary length code generated by the PN generating means in a preset bit length, and is characterized in that the address of the above-described address generating means is successively updated based on a result from the above-described comparison means, and an address at the end of comparison is output as pseudo noise information.
Also, the above-described address generating means can be constructed so that an address value in which an MSB is one and other bits are zero is set as an initial value, and in case that the above-described binary length code is larger than a comparison result of the above-described comparison means, one is hold as a value of the above-described MSB, and in case that the above-described binary length code is smaller than a comparison result of the above-described comparison means, a value of the above-described MSB is set as zero, and subsequently, a value of the next digit bit of the above-described MSB is set as one, and in case that the above-described binary length code is larger than a comparison result of the above-described comparison means, one is hold as a value of the above-described next digit bit, and in case that the above-described binary length code is smaller than a comparison result of the above-described comparison means, processing for making a value of the above-described next digit bit zero is continued until an LSB, and a final address value is output as pseudo noise information.
A multi-dimensional pseudo noise generating circuit for soft-decision decoding of the present invention for accomplishing the above-described objective is characterized by having:
a first pseudo noise generating circuit having first PN generating means for generating a signal of binary length code, a first memory in which a threshold level based on accumulative probability distribution function obtained by integrating predetermined probability density function is stored, first address generating means for generating an address of the above-described first memory, and first comparison means for comparing a data read from the above-described first memory with the binary length code generated by the PN generating means in a preset bit length, wherein the address of the above-described first address generating means is successively updated based on a result from the above-described first comparison means, and an address at the end of comparison is output; and
a second pseudo noise generating circuit having second PN generating means for generating a signal of binary length code, a second memory in which a threshold level based on accumulative probability distribution function obtained by integrating predetermined probability density function is stored, second address generating means for generating an address of the above-described second memory, and second comparison means for comparing a data read from the above-described second memory with the binary length code generated by the second PN generating means in a preset bit length, wherein the address of the above-described second address generating means is successively updated based on a result from the above-described second comparison means and an output from the above-described first pseudo noise generating circuit, and an address at the end of comparison is output as pseudo noise information.
In addition, the above-described first and second address generating means can be constructed so that an address value in which an MSB is one and other bits are zero is set as an initial value, and in case that the above-described binary length code is larger than a comparison result of the above-described comparison means, one is hold as a Value of the above-described MSB, and in case that the above-described binary length code is smaller than a comparison result of the above-described comparison means, a value of the above-described MSB is set as zero, and subsequently, a value of the next digit bit of the above-described MSB is set as one, and in case that the above-described binary length code is larger than a comparison result of the above-described comparison means, one is hold as a value of the above-described next digit bit, and in case that the above-described binary length code is smaller than a comparison result of the above-described comparison means, processing for making a value of the above-described next digit bit zero is continued until a lower bit, and a final address value is output as pseudo noise information.
Also, the above-described second pseudo noise generating circuit has a plurality of memories of which threshold levels stored therein are different from each other, and a selector for selecting a predetermined memory out of the above-described plurality of memories based on an output from the above-described first pseudo noise generating circuit, and
the above-described second comparison means can be constructed so as to compare a threshold level output from the above-described selector with the binary length code generated by the above-described second PN generating means in a preset bit length.
Moreover, the multi-dimensional pseudo noise generating circuit can be constructed so as to have a plurality of the above-described first pseudo noise generating circuits, and
so that an address of the second address generating means of the above-described second pseudo noise generating circuit is successively updated based on a result from the above-described second comparison means and outputs from the above-described plurality of first pseudo noise generating circuits, and an address at the end of comparison is output as pseudo noise information.
A multi-dimensional pseudo noise generating circuit for soft-decision decoding of the present invention for accomplishing the above-described objective is characterized by having:
a first pseudo noise generating circuit having first PN generating means for generating a signal of binary length code, a first memory in which a threshold level based on accumulative probability distribution function obtained by integrating predetermined probability density function is stored, first address generating means for generating an address of the above-described first memory, and first comparison means for comparing a data read from the above-described first memory with the binary length code generated by the PN generating means in a preset bit length, wherein the address of the above-described first address generating means is successively updated based on a result from the above-described first comparison means, and an address at the end of comparison is output;
a second pseudo noise generating circuit having second PN generating means for generating a signal of binary length code, a second memory in which a threshold level based on accumulative probability distribution function obtained by integrating predetermined probability density function is stored, second address generating means for generating an address of the above-described second memory, and second comparison means for comparing a data read from the above-described second memory with the binary length code generated by the second PN generating means in a preset bit length, wherein the address of the above-described second address generating means is successively updated based on a result from the above-described second comparison means and an output from the above-described first pseudo noise generating circuit, and an address at the end of comparison is output; and
multiplication means for multiplying an output from the above-described first pseudo noise generating circuit by an output from the above-described second pseudo noise generating circuit, and outputting a result of this multiplication as pseudo noise information.
In addition, the above-described first and second address generating means can be constructed so that an address value in which an MSB is one and other bits are zero is set as an initial value, and in case that the above-described binary length code is larger than a comparison result of the above-described comparison means, one is hold as a value of the above-described MSB, and in case that the above-described binary length code is smaller than a comparison result of the above-described comparison means, a value of the above-described MSB is set as zero, and subsequently, a value of the next digit bit of the above-described MSB is set as one, and in case that the above-described binary length code is larger than a comparison result of the above-described comparison means, one is hold as a value of the above-described next digit bit, and in case that the above-described binary length code is smaller than a comparison result of the above-described comparison means, processing for making a value of the above-described next digit bit zero is continued until an LSB, and a final address value is output as pseudo noise information.
Also, the above-described second pseudo noise generating circuit has a plurality of memories of which threshold levels stored therein are different from each other, and a selector for selecting a predetermined memory out of the above-described plurality of memories based on an output from the above-described first pseudo noise generating circuit, and
the above-described second comparison means can be constructed so as to compare a threshold level output from the above-described selector with the binary length code generated by the above-described second PN generating means in a preset bit length.